Automatic hardware generation for the Molen reconfigurable architecture: a G721 case study

The advantages of the reconfigurable technology in terms of performance have been widely recognized. However, programming reconfigurable systems and designing hardware accelerators for them is not a trivial task. The Molen paradigm provides an easy to use approach to couple a General Purpose Processor (GPP) with custom designed reconfigurable accelerators both at program level and at hardware design level. In this case study, we illustrate the entire design flow to demonstrate how one can use the DelftWorkbench Automated Reconfigurable VHDL Generator (DWARV) tool, the Molen compiler and the Molen reconfigurable co-processor to accelerate a C application code in hardware. As a case study application, the G721 audio encoder is used. The implementation platform is a Xilinx VirtexII Pro XC2VP30-7 FPGA, which integrates two PowerPC 405 processors. The experimental results obtained after employing the described design flow suggest an overall application speedup of 2.7 times over a pure software implementation. Keywords— Reconfigurable processors, FPGA, Molen paradigm, Automatic HDL generation